Cache memories are high-speed memories that facilitate fast retrieval of data or instructions. Typically, cache memories are relatively expensive and are characterized by a small size, especially in comparison to external memories. Great Britain patent 2389206 titled “cache control using queues to buffer requests and date” and European patent application EP0883065A2 titled “Non-blocking pipelined cache” illustrate various prior art cache memories.
Typically, a cache memory includes multiple cache resources. Each cache resource is preceded by a dedicated arbitrator that arbitrates between different requests to access this cache resource. Cache resources can include data memory, tag memory, hit/miss calculation logic, dirty/valid memory, and the like.
FIG. 1 illustrates a prior art cache memory 10 and its environment. Cache memory 10 is connected to multiple access generators 12(1)-12(M). An access generator can generate an access request. Typical access generators include processors, controllers, Direct Memory Access controllers and the like.
Cache memory 10 includes multiple arbitrators 16(1)-16(N) and multiple cache resources 18(1)-18(N). Each cache resource is preceded by an arbitrator.
The arbitrators are usually complex and tailored to each cache resource. The same access generator can be connected in parallel to multiple arbitrators. If a cache memory is expected to support a new access generator then multiple arbitrators should be re-designed. In addition, having a tailored arbitrator per cache resource is not efficient.
There is a need to provide a system and a method that can effectively manage access requests of different types.